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| INTEGRATED CIRCUITS SSTL16877 14-bit SSTL_2 registered driver with differential clock inputs Product specification Supersedes data of 2000 Apr 11 2000 Apr 20 Philips Semiconductors Philips Semiconductors Product specification 14-bit SSTL_2 registered driver with differential clock inputs SSTL16877 FEATURES * Stub-series terminated logic for 2.5 V VDDQ (SSTL_2) * Optimized for DDR (Double Data Rate) SDRAM applications * Supports SSTL_2 signal inputs and outputs * Flow-through architecture optimizes PCB layout * Meets SSTL_2 class I and class II specifications * Latch-up protection exceeds 500mA per JEDEC Std 17 * ESD protection exceeds 2000 V per MIL STD 833 Method 3015 and 200 V per Machine Model PIN CONFIGURATION Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ 1 2 3 4 5 6 7 8 9 48 D1 47 D2 46 GND 45 VCC 44 D3 43 D4 42 D5 41 D6 40 D7 39 CLK- 38 CLK+ 37 VCC 36 GND 35 VREF 34 RESET 33 D8 32 D9 31 D10 30 D11 29 D12 28 VCC 27 GND 26 D13 25 D14 * Full DDR solution provided when used with PCK877 and CBT3867 DESCRIPTION The SSTL16877 is a 14-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ must not exceed VCC. Inputs are SSTL_2 type with VREF normally at 0.5*VDDQ. The outputs support class I which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTL16877 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 166 MHz will have a burst rate of 333 MHz. The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTL16877 is intended to be used for SSTL_2 input and output signals. The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential to be compatible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CLK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the LOW state will assume that all registers are reset to the LOW state and all outputs drive a LOW signal as well. Q6 10 Q7 11 VDDQ 12 GND 13 Q8 14 Q9 15 VDDQ 16 GND 17 Q10 18 Q11 19 Q12 20 VDDQ 21 GND 22 Q13 23 Q14 24 SW00311 QUICK REFERENCE DATA GND = 0 V; Tamb = 25C; tr =tf v2.5 ns SYMBOL tPHL/tPLH CI PARAMETER Propagation delay; CLK to Qn Input capacitance CONDITIONS CL = 30 pF; VDDQ = 2.5 V VCC = 2.5 V TYPICAL 2.4 2.9 UNIT ns pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD VCC2 x fi ) (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. ORDERING INFORMATION PACKAGES 48-Pin Plastic TSSOP Type I TEMPERATURE RANGE 0C to +70C ORDER CODE SSTL16877 DGG DWG NUMBER SOT362-1 2000 Apr 20 2 853-2198 23523 Philips Semiconductors Product specification 14-bit SSTL_2 registered driver with differential clock inputs SSTL16877 PIN DESCRIPTION PIN NUMBER 34 48, 47, 44, 43, 42, 41, 40, 33, 32, 31, 30, 29, 26, 25 1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24 35 3, 8, 13, 17, 22, 27, 36, 46 28, 37, 45 4, 9, 12, 16, 21 38 39 SYMBOL RESET NAME AND FUNCTION LVCMOS asynchronous master reset (Active LOW) LOGIC DIAGRAM RESET VREF D1 REGISTER Q1 D2 D1 - D14 SSTL_2 data inputs AD REGISTER Q2 REGISTER Q3 Q1 - Q14 VREF GND VCC VDDQ CLK+ CLK- SSTL_2 data outputs SSTL_2 input reference level D4 REGISTER Q4 D5 REGISTER Q5 Ground (0 V) Positive supply voltage Output supply voltage D7 REGISTER D6 REGISTER Q6 Differential clock inputs D8 REGISTER Q7 Q8 FUNCTION TABLE INPUTS RESET L H H CLK X CLK X L or H D X H L X OUTPUT Q D10 D9 REGISTER Q9 L H L Q0 D12 D11 REGISTER Q10 REGISTER Q11 H L or H H = High voltage level L = High voltage level = High-to-Low transition = Low-to-High transition X = Don't care REGISTER Q12 D13 REGISTER Q13 D14 REGISTER Q14 CLK+ CLK- SW00312 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK VI IOK VOUT IO OUT PARAMETER DC supply voltage DC input diode current DC input voltage3 DC output diode current DC output voltage3 DC output current Continuous current4 VO < 0 Note 3 VO = 0 to VDDQ VCC, VDDQ, or GND -0.5 VI < 0 -0.5 CONDITION LIMITS MIN -0.5 MAX +4.6 -50 VDDQ + 0.5 -50 VDDQ + 0.5 50 100 UNIT V mA V mA V mA TSTG Storage temperature range -65 +150 C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 4. The continuous current at VCC, VDDQ, or GND should not exceed 100 mA. 2000 Apr 20 3 Philips Semiconductors Product specification 14-bit SSTL_2 registered driver with differential clock inputs SSTL16877 RECOMMENDED OPERATING CONDITIONS1 SYMBOL VCC VDDQ VREF VTT VI VIH VIL VIH VIL IOH IOL PARAMETER Supply voltage Output supply voltage Reference voltage (VREF = 0.5 x VDDQ) Termination voltage Input voltage AC HIGH-level input voltage AC LOW-level input voltage DC HIGH-level input voltage DC LOW-level input voltage HIGH-level output current LOW-level output current 0 All inputs All inputs All inputs All inputs VREF + 180 mV VSS - 0.5 V TEST CONDITIONS MIN 2.3 2.3 1.15 VREF - 40 mV 0 VREF + 350 mV VREF - 350 mV VDDQ + 0.5 V VREF - 180 mV -20 20 70 TYP 2.5 2.5 1.25 VREF MAX 2.7 2.7 1.35 VREF + 40 mV VCC UNIT V V V V V V V V V mA mA C Tamb Operating free-air temperature range NOTE: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL VIK VOH PARAMETER I/O supply voltage HIGH level output voltage TEST CONDITIONS VCC = 2.3 V; II = -18 mA VCC = 2.3 V to 2.7 V; IOH = -100 A VCC = 2.3 V; IOH = -8 mA VCC = 2.3 V; IOH = -16 mA VCC = 2.3 V to 2.7 V; IOL = -100 A VOL VCMR VPP LOW level output voltage CLK, CLK CLK, CLK Data inputs RESET inputs, II CLK, CLK CLK VREF ICC Quiescent supply current CLK and CLK in opposite o osite state1 VCC = 2.3 V; IOL = -8 mA VCC = 2.3 V; IOL = -16 mA Common mode range for reliable performance Minimum peak-to-peak input to ensure logic state VCC = 2.7 V ; VI = 1.7 V or 0.8 V VCC = 2.7 V ; VI = 2.7 V or 0 V VCC = 2.7 V ; VI = 1.7 V or 0.8 V VCC = 2.7 V ; VI = 2.7 V or 0 V VCC = 2.7 V VCC = 2.7 V ; VI = 1.7 V or 0.8 V VCC = 2.7 V ; VI = 2.7 V or 0 V VREF = 1.15V or 1.35V 1 15V 1 35V VREF = 1.15V or 1.35V 1 15V 1 35V VREF = 1.15V or 1.35V 0.97 360 0.01 0.01 0.05 0.05 0.05 12 10 5 5 5 5 5 25 mA 25 VCC - 0.2 1.95 1.95 2.3 2.2 2.1 0.002 0.14 0.30 0.2 0.35 0.35 1.53 V mV A A A V Temp = 0C to +70C MIN TYP2 MAX -1.2 V UNIT NOTES: 1. When CLK and CLK are HIGH, typical ICC = 25 mA. 2. All typical values are at VCC = 3.3 V and Tamb = 25C (unless otherwise specified). 2000 Apr 20 4 Philips Semiconductors Product specification 14-bit SSTL_2 registered driver with differential clock inputs SSTL16877 TIMING REQUIREMENTS Over recommended operating conditions; Tamb = 0_C to +70_C (unless otherwise noted) (see Figure 1) LIMITS SYMBOL PARAMETER TEST CONDITIONS VCC = 2.5 V 0.2 V MIN fclock tw tsu th Clock frequency Pulse duration, CLK, CLK HIGH or LOW Data before CLK, CLK Setup time Hold time RESET HIGH before CLK, CLK 1.0 0.2 0.8 1.2 ns ns MAX 200 MHz ns UNIT SWITCHING CHARACTERISTICS Over recommended operating conditions; Tamb = 0_C to +70_C; VDDQ = 2.3 - 2.7 V and VDDQ does not exceed VCC. Class I, VREF = VTT = VDDQ x 0.5 and CL = 10 pF (unless otherwise noted) (see Figure 1) LIMITS SYMBOL FROM (INPUT) Maximum clock frequency CLK and CLK RESET Q Q TO (OUTPUT) VCC = 2.5 V 0.2 V MIN fmax tPLH/tPHL tPHL 200 1.0 2.0 3.5 4.0 MAX MHz ns ns UNIT 184/200-pin DDR SDRAM DIMM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM BACK SIDE CBT CBT CBT CBT CBT CBT CBT CBT CBT CBT3867 (9) SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM FRONT SIDE SSTL16877 SSTL16877 PCK877 The PLL clock distribution device and SSTL registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation SDRAM SW00502 2000 Apr 20 5 Philips Semiconductors Product specification 14-bit SSTL_2 registered driver with differential clock inputs SSTL16877 PARAMETER MEASUREMENT INFORMATION AC WAVEFORMS VIH CLK VREF VREF INPUT VIL tPLH tPHL VOH OUTPUT VREF VREF VREF VREF VIL tW VIH SW00339 Waveform 3. Pulse duration VOL SW00338 Waveform 1. Propagation delay times inverting and non-inverting outputs TIMING INPUT VREF VIH VIL RESET VREF VIL tPHL OUTPUT VREF VOL VOH VIL DATA INPUT VREF VREF VIH tsu th VIH SW00402 SW00340 Waveform 2. Propagation delay RESET to output. Waveform 4. Setup and hold times TEST CIRCUIT VTT TEST POINT 25 = SSTL_2 Class II 50 = SSTL_2 Class I CL = 10pF or 30pF 50pF 500 25 SW00336 Figure 2. NOTES: CL includes probe and jig capacitance All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, tr 1.25ns/V, tf 1.25ns/V. The outputs are measured one at a time with one transition per measurement. VTT = VREF = VDDQ x 0.5 50pF SW00335 Figure 3. SW00337 Figure 1. Load circuitry 2000 Apr 20 6 Philips Semiconductors Product specification 14-bit SSTL_2 registered driver with differential clock inputs SSTL16877 TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 2000 Apr 20 7 Philips Semiconductors Product specification 14-bit SSTL_2 registered driver with differential clock inputs SSTL16877 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 04-00 Document order number: 9397 750 07086 Philips Semiconductors 2000 Apr 20 8 |
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